This invention relates generally to computer systems more particularly to memory access in a computer system.
As is known in the art, computer systems generally include one or more central processing units (CPUs), memory, and peripheral devices such as disk drives. Typical modem day computers use a modular design in order to construct computer systems of varying configurations. That is, the CPUs will typically be physically located on one module while the memory subsystems and peripheral device controllers will be physically located in separate modules. Each module will then be plugged into a backplane or bus over which the individual modules communicate.
Communication between various modules occurs during so called "bus cycles". A bus cycle is the time required for a transaction to occur over the bus. For example a read from memory by a central processor includes assertion of command and address data on the bus, receipt of the command and address data by the memory module, assertion of the data read from the memory onto the bus and receipt of that data by the CPU. In so-called synchronous computer systems, operations occurring within the system are controlled by various clocks and the time required to complete a bus cycle is dictated by a combination of the CPU clock speed, the bus clock speed and the clock speed of the other transacting module.
In synchronous computer systems, there are two types of modules provided with respect to how clock signals from the clock circuit are used. One type of module, for example an Input/Output (I/O) module or a processor module, synchronous logic on the module will adapt to changes in clock frequency and, provided propagation delays and set up and hold time criteria are met for the different clock frequencies, the module will operate in a synchronous manner. A second type of module, for example a memory module, uses a clock signal to initiate or control fixed time devices. That is, a typical memory module populated with a plurality of Dynamic Random Access Memories (DRAM) provides control signals, in particular Row Address Strobe (RAS) and Column Address Strobe (CAS), which have a fixed time relationship with the number of clock periods or cycles provided by the associated clock circuit.
For example, in the case of a fixed cycle time memory module, if the bus and the memory were allowed to run at their optimized speeds of 10 nanoseconds, and a typical memory access required 12 clock cycles to complete a transaction, the associated memory latency would be 120 nanoseconds. If however, for any reason, it was necessary to slow the bus to operate at 16 nanoseconds, a memory access would take 192 nanoseconds to complete (i.e., 16 nanoseconds/cycle.times.12 cycles). This represents an increase of 72 nanoseconds per memory access. Therefore it can be seen that slowing the system bus to accommodate the CPU processing speed has a detrimental effect on overall performance of a computer system, It also decreases the availability of the memory to other bus devices by the same increment of time (72 nanoseconds in the above example). This therefore decreases the overall bandwidth capability of the memory linearly with the increase in clock cycle time.
The memory devices used in current main memory system designs, DRAMs, are fixed timing devices relative to their primary clock's RAS and CAS. That is, these DRAMs do not operate strictly in terms of the "system clock", but have fixed timing parameters related to the control signals RAS and CAS whose minimum timing is equivalent to one or more bus clocks for the above example.
In high speed systems (one with fast clocks--10 nanoseconds in the above example), RAS and CAS would typically be driven as outputs from a finite state machine (FSM) on only one edge of the system clock and with the FSM state transitions occurring on that same clock edge (typically the rising clock edge). If the bus clock could be varied (particularly increased in duration, 16 nanoseconds or more in our example) and this fixed timing relationship remained, the timing for RAS and CAS would become stretched out, leading to a delay in asserting the control signals to retrieve such information as READ DATA. Also delayed would be any communication signals to the bus that indicate that READ DATA is available thereby causing a further delay. Another artifact of this clock delay is that the DRAMs would be "busy" for a longer period of time for all transaction types (READ, WRITE, REFRESH). This then leads to an overall decrease in available memory bandwidth (in transactions per second) since each transaction takes the same number of bus clocks on the memory regardless of the time per clock cycle. So, a longer clock cycle means fewer of them per second and thus fewer transactions per second.